Shift Register ( Vhdl )

Shift Register ( Vhdl )

In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the 'data' input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the 'bit array' stored in it, 'shifting in' the data present at its input and 'shifting out' the last bit in the array, at each transition of the clock input.

More generally, a shift register may be multidimensional, such that its 'data in' and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as 'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also 'bidirectional' shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a 'circular shift register'

so the Vhdl code of  a shift register :

library ieee ;
use ieee.std_logic_1164.all ;
---------------------------------------------------------------------------------
entity shiftReg is
  port(
    p : in std_logic_vector(7 downto 0 ) ;
    d : in std_logic ;
    clk : in std_logic ;
    reset : in std_logic ;
    ld :  in std_logic ;
    qout : out std_logic_vector ( 7 downto 0 ) ;
    q : out std_logic
  );
end entity ;



architecture arch of shiftReg is
signal qout1 : std_logic_vector ( 7 downto 0 ) ;
signal q1 :  std_logic ;
begin
process ( clk , reset)
  begin
    if ( reset = '1' ) then
      qout1 <= "00000000";
      q1 <= '0' ;
    elsif (clk ' event and clk = '1' ) then
      if (ld = '1') then 
        qout1 <= p ;
      else 
        qout1 <= d & qout1(7 downto 1) ;
        q1 <= qout1(0) ;
    end if ;
  end if ;
end process ;
 qout <=  qout1 ;
 q <= q1 ;
 end arch ;

simulation results with modelSim :